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? no products described or contained herein are intende d for use in surgical implants, life-support systems, aerospace equipment, nuclear power c ontrol systems, vehicles, disaster/c rime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ? anyone purchasing any products described or containe d herein for an above-mentioned use shall: 1) accept full responsibility and indemnify and defend sanyo electric co., ltd., its affiliates, subsidiaries and distributors and all their officer s and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: 2) not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on sanyo electric co., ltd., its affiliates, subsidiaries and di stributors or any of their officers and employees jointly or severally. ? information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. s anyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or an y infringements of intellectual property rights or other rights of third parties. this product incorporates technology licen sed from silicon storage technology inc. this catalog provides information as of feb 2002. specifica tions and information herein are subject to change without notice. sanyo electric co., ltd. semiconductor company. system-business div. 1-1-1, sakata oizumi-machi, gunma, japan ver.1.00 apr 03 microcomputer business unit t.kitamura 1/27 it 8 bit single chip microcontroller preliminary LC87F57C8A LC87F57C8A 8-bit single chip microcontroller incorporat ing 128k-byte feprom and 3k-byte ram on chip. overview the LC87F57C8A is 8-bit single chip microcontroller with the following one-chip features: - cpu : operable at a minimum bus cycle time of 100ns - on-chip flash rom capacity : 128k bytes (on-board rewritable) - on-chip ram capacity : 3k bytes - two high performance 16-bit timer/counters (can be divided into 8 bit timers) - four 8-bit timers with prescalers - timer for use as date/time clock - one synchronous serial i/o port (with au tomatic block transmit/receive function) - one asynchronous/synchronous serial i/o port - 12-bit pwm 2 - 12-channel 8-bit ad converter - high speed 8-bit parallel interface - high speed clock counter - system clock divider - 20-source 10-vectored interrupt system features (1) read only memory (flash rom) - single 5v power supply, on-board writeable - block erase in 128 byte units - 131072 8 bits (LC87F57C8A) (2) bus cycle time - 100ns (10mhz) note: bus cycle time indicates the speed to read rom.
LC87F57C8A 2/27 ver.1.00 (3) minimum instruction cycle time : 300ns (10mhz) (4) ports - input/output ports input/output programmable for each b it individually 43 (p1n, p2n, p70 to p73, p8n, pan, pbn, pcn) data direction programmable in nibble units 8 (p0n) - input ports 2 (xt1, xt2) - pwm output ports 2 (pwm0, pwm1) - oscillator pins 2 (cf1, cf2) - reset pin 1 ( res ) - power supply 6 (vss1 to 3, vdd1 to 3) (5) timer - timer 0 : 16-bit timer/counter with capture register mode 0: two 8-bit timers with programmable 8-bit prescaler and 8-bit capture register mode 1: 8-bit timer with 8-bit programmable prescaler and 8-bit capture register + 8-bit counter with 8-bit capture register mode 2: 16-bit timer with 8-bit programmable prescaler and 16-bit capture register mode 3: 16-bit counter with 16-bit capture register - timer 1 : pwm/16-bit timer/counter with toggle output mode 0: 8-bit timer (with toggle output) + 8-bit timer/counter (with toggle output) mode 1: two 8-bit pwm mode 2: 16-bit timer/counter (with toggle output) toggle output is also possible by using the lower order 8 bits. mode 3: 16 bit timer (with toggle output) the lower order 8 bits can be used as pwm output. - timer 4: 8-bit timer with 6-bit prescaler - timer 5: 8-bit timer with 6-bit prescaler - timer 6: 8-bit timer with 6-bit prescaler - timer 7: 8-bit timer with 6-bit prescaler - base timer 1. clock for the base timer is selectable fro m sub-clock (32.768khz crystal oscillation), system clock or programmable prescaler output of timer 0. 2. there can be five separate interrupt sources. (6) high speed clock counter 1. maximum of 20mhz possible (when using a 10mhz main clock). 2. real-time output (7) serial interface - sio 0: 8 bit synchronous serial interface 1. lsb first/msb first-function available 2. an internal 8-bit baud-rate generator (maximum transmit clock period 4/3 t cyc ) 3. consecutive automatic data communication (1 - 256 bits) - sio 1: 8 bit asynchronous/synchronous serial interface mode 0: synchronous 8 bit serial io (2-wire or 3-wire, transmit clock 2 - 512 t cyc ) mode 1: asynchronous serial io (half duplex, 8 data bits, 1 stop bit, baud-rate 8 - 2048 t cyc ) mode 2: bus mode 1 (start bit, 8 data bits, transmit clock 2 - 512 t cyc ) mode 3: bus mode 2 (start detection, 8 data bits, stop detection)
LC87F57C8A ver.1.00 3/27 (8) ad converter - 12-channel 8-bit ad converter (9) pwm - 2 channel synchronous variable 12 bit pwm (10) parallel interface - rs, rd , wr , cs0 outputs (polarity can be toggled) - read/write possible in 1 t cyc (11) remote receiver circuit (sha re with p73/int3/t0in terminal) - noise rejection function (the filtering time of the noise rejection filter (1t cyc /32 t cyc /128 t cyc ) can be switched by program.) (12) watchdog timer - external rc circuit is required. - interrupt or system reset is activated when the timer overflows. (13) interrupts - 20-source and 10-vectored interrupt function: 1. three interrupt priorities, low (l), high (h ) and highest (x) are supported with multi-level nesting possible. during interrupt handling, an e qual or lower level interrupt request is refused. 2. if interrupt requests for two or more vector addresses occur at once, the higher level interrupt takes precedence. in the case of e qual priority levels, the vector with the lowest address takes precedence. no. vector selectable level interrupt signal 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l/int4 4 0001bh h or l int3/int5/base timer 5 00023h h or l t0h 6 0002bh h or l t1l/t1h 7 00033h h or l sio0 8 0003bh h or l sio1 9 00043h h or l adc/t6/t7 10 0004bh h or l port 0/t4/t5/pwm0, pwm1 ? priority level: x > h > l ? for equal priority levels, vector with lowest address takes precedence. (14) subroutine stack levels - a maximum of 1536 levels (set stack inside ram) (15) multiplication and division - 16 bits 8 bits (5 instruction-cycle times) - 24 bits 16 bits (12 instruction-cycle times) - 16 bits 8 bits (8 instruction-cycle times) - 24 bits 16 bits (12 instruction-cycle times) (16) oscillation circuits - built-in rc oscillation circuit used for the system clock - cf oscillation circuit used for the system clock - crystal oscillation circuit used for the system clock - built-in frequency variable rc oscillation circuit used for the system clock (17) system clock divider - operable on the lowest power consumption - minimum instruction cycle time (300ns, 600ns, 1.2s, 4.8s, 9.6s, 19.2s, 38.4s, 76.8s can be switched by program (when using 10mhz main clock)
LC87F57C8A 4/27 ver.1.00
LC87F57C8A ver.1.00 5/27 (18) standby function - halt mode the halt mode stops program execution while the peripheral circuits keep operating and minimizes power consumption. this operation mode can be released by a system reset or an interrupt request. - hold mode the hold mode stops program execution and all oscillation circuits: cf, rc and crystal oscillations. this mode can be re leased by the following conditions. 1. supply "l" level to the reset terminal ( res ) 2. supply the selected level to at lease one of int0, int1, int2, int4 int5. 3. supply an interrupt condition to port 0. - x?tal hold mode the x?tal hold mode stops program execution and all peripheral circuits except for the base timer. the crystal oscillator maintains its state at hold mode inception. this mode can be released by the following conditions. 1. supply "l" level to the reset terminal ( res ). 2. supply the selected level to at least one of int0, int1, int2, int4, int5 3. supply an interrupt condition to port 0. 4. supply an interrupt condition to the base timer circuit. (19) shipping form - qip64e - sqfp64 (20) development tools - evaluation (eva) chip : lc876093 - emulator : eva62s + ecb876600a + sub875700 + pod64qfp or pod64sqfp - flash rom writer adapter :w87f50256q(qip64e),w87f57256sq(sqfp64)
LC87F57C8A 6/27 ver.1.00 pin assignment pa5/rs pa4/rd# pa3/wr# pa2/cs0# pc0/a0 pc1/a1 pc2/a2 pc3/a3 pc4/a4 pc5/a5 pc6/a6 pc7/a7 vdd3 vss3 pb0/d0 pb1/d1 pb2/d2 pb3/d3 pb4/d4 pb5/d5 pb6/d6 pb7/d7 p27/int5/t1in p26/int5/t1in p25/int5/t1in p24/int5/t1in p23/int4/t1in p22/int4/t1in p21/int4/t1in p20/int4/t1in p07/an7 p06/an6 p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in p73/int3/t0in res# xt1/an10 xt2/an11 vss1 cf1 cf2 vdd1 p80/an0 p81/an1 p82/an2 p10/so0 p11/si0/sb0 p12/sck0 p13/so1 p14/si1/sb1 p15/sck1 p16/t1pwml p17/t1pwmh/buz pwm1 pwm0 vdd2 vss2 p00 p01 p02 p03/an3 p04/an4 p05/an5 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 48 lc87f5700a qip64e sqfp64 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
LC87F57C8A ver.1.00 7/27 qip /sqfp name qip /sqfp name 1 p12/sck0 33 pb1/d1 2 p13/so1 34 pb0/d0 3 p14/si1/sb1 35 vss3 4 p15/sck1 36 vdd3 5 p16/t1pwml 37 pc7/a7 6 p17/t1pwmh/buz 38 pc6/a6 7 pwm1 39 pc5/a5 8 pwm0 40 pc4/a4 9 vdd2 41 pc3/a3 10 vss2 42 pc2/a2 11 p00 43 pc1/a1 12 p01 44 pc0/a0 13 p02 45 pa2/cs0# 14 p03/an3 46 pa3/wr# 15 p04/an4 47 pa4/rd# 16 p05/an5 48 pa5/rs 17 p06/an6 49 p70/int0/t0lcp/an8 18 p07/an7 50 p71/int1/t0hcp/an9 19 p20/int4/t1in 51 p72/int2/t0in 20 p21/int4/t1in 52 p73/int3/t0in 21 p22/int4/t1in 53 res# 22 p23/int4/t1in 54 xt1/an10 23 p24/int5/t1in 55 xt2/an11 24 p25/int5/t1in 56 vss1 25 p26/int5/t1in 57 cf1 26 p27/int5/t1in 58 cf2 27 pb7/d7 59 vdd1 28 pb6/d6 60 p80/an0 29 pb5/d5 61 p81/an1 30 pb4/d4 62 p82/an2 31 pb3/d3 63 p10/so0 32 pb2/d2 64 p11/si0/sb0
LC87F57C8A 8/27 ver.1.00 system block diagram interrupt control standby control ir pla flash rom pc sio0 sio1 timer 0 timer 1 bus interface port 1 port 0 port 7 port 8 adc port 2 int4,,5 parallel interface port a port b port c acc b register c register psw rar ram stack pointer watch dog timer pwm0 pwm1 base timer alu int0-3 noise rejection filter timer 4 timer 5 timer 6 timer 7 cf rc xtal clock generator mrc
LC87F57C8A ver.1.00 9/27 pin description name i/o function description option vss1, vss2 vss3 - power terminal (-) no vdd1, vdd2 vdd3 - power terminal (+) no port 0 p00 - p07 i/o ? 8-bit input/output port ? data direction programmable in nibble units ? pull-up resistor provided/not provi ded (specified in nibble units) ? hold release input ? port 0 interrupt input ? ad converter input port : an3 (p03)- an7 (p07) yes port 1 p10 - p17 i/o ?8-bit input/output port ? data direction programmable for each bit individually ? pull-up resistor provided/not provided (specified by bit) ? other functions p10: sio0 data output p11: sio0 data input, bus input/output p12: sio0 clock input/output p13: sio1 data output p14: sio1 data input, bus input/output p15: sio1 clock input/output p16: timer 1 pwml output p17: timer 1 pwmh output/buzzer output yes port 2 ? 8-bit input/output port ? data direction programmable for each bit individually ? pull-up resistor provided/not provided (specified by bit) ? other functions p20-p23: int4 input/hold release input/timer 1 event input/timer 0l capture input/timer 0h capture input p24-p27: nt5 input/hold release input/timer 1 event input/timer 0l capture input/timer 0h capture input ? interrupt detection style rising falling rising/ falling h level l level int4 enable enable enable disable disable int5 enable enable enable disable disable p20 - p27 i/o yes port 7 ? 4-bit input/output port ? data direction programmable for each bit individually ? pull-up resistor provided/not provided (specified by bit) ? other functions p70: int0 input/hold release input/t imer 0l capture input/output for watchdog timer p71: int1 input/hold release input/timer 0h capture input p72: int2 input/hold release input/timer 0 event input/timer0l capture input p73: int3 input with noise filter/ti mer 0 event input/timer 0h capture input ? interrupt detection style no rising falling rising/ falling h level l level int0 enable enable disable enable enable int1 enable enable disable enable enable int2 enable enable enable disable disable int3 enable enable enable disable disable p70 - p73 i/o ? ad converter input port : an8 (p70), an9 (p71) (continued)
LC87F57C8A 10/27 ver.1.00 name i/o function description option port 8 p80 - p82 i/o ? 3-bit input/output port ? data direction programmable for each bit individually ? other functions p80-p82 : ad converter input port no port a pa2 - pa5 i/o ? 4-bit input/output port ? data direction programmable for each bit individually ? pull-up resistor provided/not provided (specified by bit) ? other functions pa2: parallel interface output cs0 pa3: parallel interface output wr pa4: parallel interface output rd pa5: parallel interface output rs yes port b pb0 - pb7 i/o ? 8-bit input/output port ? data direction programmable for each bit individually ? pull-up resistor provided/not provided (specified by bit) ? other functions pb0-pb7 : parallel interface data input/output, address output yes port c pc0 - pc7 i/o ? 8-bit input/output port ? data direction programmable for each bit individually ? pull-up resistor provided/not provided (specified by bit) ? other functions pc0-pc7 : parallel interface address output yes pwm0 o pwm0 output port no pwm1 o pwm1 output port no res i reset terminal no xt1 i ? input terminal for 32.768khz x'tal oscillation ? other function an10 : ad converter input port general input port when not in use, connect terminal to vdd1. no xt2 i/o ? output terminal for 32.768khz x'tal oscillation ? other function an11 : ad converter input port general input port when not in use, set as oscillation and leave terminal open no cf1 i input terminal fo r ceramic resonator no cf2 o output terminal for ceramic resonator no
LC87F57C8A ver.1.00 11/27 port output configuration output configuration and pull-up resistor options are shown in the following table. input is possible even when a port is in output mode. terminal option applies to: option output format pull-up resistor 1 cmos programmable (note 1) p00 - p07 each bit 2 nch-open drain none 1 cmos programmable p10 - p17 p20 - p27 each bit 2 nch-open drain programmable 1 cmos programmable pa2 - pa5 pb0 - pb7(*) pc0 - pc7 each bit 2 nch-open drain programmable p70 - none nch-open drain programmable p71 - p73 - none cmos programmable p80 - p82 - none nch-open drain none pwm0, pwm1 - none cmos none xt1 - none input only none xt2 - none output for 32.768khz crystal oscillation none note 1 programmable pull-up resistor of port 0 is specified in nibble units (p00 - p03, p04 - p07). (*) when in parallel interface mode, pb0 - pb7 output format is cmos, regardless of any selected option. note: to reduce vdd signal noise and to increase the duration of the backup battery supply, vss1, vss2, and vss3 should connect to each othe r and they should also be grounded. example 1 : during backup in hold mode, port output ?h? level is supplied from the back-up capacitor. vss1 vss2 vss3 vdd1 vdd2 vdd3 power supply back-up ca p acitor lsi
LC87F57C8A 12/27 ver.1.00 example 2 : during backup in hol d mode, output is not held hi gh and its value in unsettled. lsi vss1 vss2 vss3 vdd1 vdd2 vdd3 power supply back-up ca p acitor
LC87F57C8A ver.1.00 13/27 1. absolute maximum ratings / ta=25c, vss1=vss2=vss3=0v limits parameter symbol pins conditions vdd[v] min. typ. max. unit supply voltage vddmax vdd1, vdd2, vdd3 vdd1=vdd2 =vdd3 -0.3 +6.5 input voltage vi(1) xt1, xt2, cf1 -0.3 vdd+0.3 output voltage vo(1) pwm0, pwm1 -0.3 vdd+0.3 input/output voltage vio(1) ? ports 0, 1, 2 ? ports 7, 8 ? ports a, b, c ? pwm0, pwm1 -0.3 vdd+0.3 v ioph(1) ? ports 0, 1, 2 ? ports a, b, c ? pwm0, pwm1 ? cmos output ? for each pin. -10 peak output current ioph(2) p71-p73 for each pin. -5 ioah(1) p71-p73 total of all pins -5 ioah(2) ? port 1 ? pwm0, pwm1 total of all pins -30 ioah(3) port 0 total of all pins -20 ioah(4) ports b,2 total of all pins -20 high level output current total output current ioah(5) ports a, c total of all pins -20 iopl(1) ? p02-p07 ? ports 1, 2 ? ports a, b, c ? pwm0, pwm1 for each pin. 20 iopl(2) p00, p01 for each pin. 30 peak output current iopl(3) ports 7, 8 for each pin. 5 ioal(1) port 7 total of all pins 15 ioal(2) port 8 total of all pins 15 ioal(3) ? port 1 ? pwm0, pwm1 total of all pins 50 ioal(4) port 0 total of all pins 70 ioal(5) ports b,2 total of all pins 40 low level output current total output current ioal(6) ports a, c total of all pins 40 ma qip64e 429 maximum power consumption pdmax sqfp64 ta= -20 to +70c 271 mw operating temperature range topg -20 70 storage temperature range tstg -55 125 c
LC87F57C8A 14/27 ver.1.00 2. recommended operating range / ta=-20c to +70c, vss1=vss2=vss3=0v limits parameter symbol pins conditions vdd[v] min. typ. max. unit 0.294s t cyc 200s 4.5 5.5 operating supply voltage range vdd(1) vdd1=vdd2 =vdd3 0.588s t cyc 200s except for on-board rewriting 2.5 5.5 hold voltage vhd vdd1=vdd2 =vdd3 ram and register data ar e kept in hold mode. 2.0 5.5 vih(1) ? ports 1, 2 ? p71-p73 ? p70 port input /interrupt 2.5 - 5.5 0.3vdd +0.7 vdd vih(2) ? ports 0, 8 ? ports a, b, c 2.5 - 5.5 0.3vdd +0.7 vdd vih(3) port 70 watchdog timer 2.5 - 5.5 0.9vdd vdd input high voltage vih(4) xt1, xt2, cf1, res 2.5 - 5.5 0.75vdd vdd vil(1) ? ports 1, 2 ? p71-p73 ? p70 port input /interrupt 2.5 - 5.5 vss 0.1vdd +0.4 vil(2) ? ports 0, 8 ? ports a, b, c 2.5 - 5.5 vss 0.15vdd +0.4 vil(5) port 70 watchdog timer 2.5 - 5.5 vss 0.8vdd -1.0 input low voltage vil(6) xt1, xt2, cf1, res 2.5 - 5.5 vss 0 .25vdd v 4.5 - 5.5 0.294 200 operation cycle time t cyc except for on-board rewriting 2.5 - 5.5 0.588 200 s ? leave cf2 pin open ? system clock divider set to 1/1 ? external clock duty=505% 4.5 - 5.5 0.1 10 ? leave cf2 pin open ? system clock divider set to 1/1 ? external clock duty=505% 2.5 - 5.5 0.1 5 ? leave cf2 pin open ? system clock divider set to 1/2 4.5 - 5.5 0.2 20.4 external system clock frequency fexcf(1) cf1 ? leave cf2 pin open ? system clock divider set to 1/2 2.5 - 5.5 0.1 10 mhz
LC87F57C8A ver.1.00 15/27 limits parameter symbol pins conditions vdd[v] min. typ. max unit fmcf(1) cf1, cf 2 10mhz ceramic resonator oscillation refer to figure 1 4.5- 5.5 10 fmcf(2) cf1, cf2 5mhz ceramic resonator oscillation refer to figure 1 2.5 - 5.5 5 fmrc rc oscillation 2.5 - 5.5 0.3 1.0 2.0 fmmrc frequency variable rc oscillation source oscillation 2.5 - 5.5 50 mhz oscillation frequency range (note1) fsx?tal xt1, xt2 32.768khz crystal resonator oscillation refer to figure 2 2.5 - 5.5 32.7 68 khz (note 1) the oscillation parameters are shown on tables 1 and 2. (note 2) vdd 4.5v is required for on-board flash rom rewriting.
LC87F57C8A 16/27 ver.1.00 3. electrical characteristics / ta=-20c to +70c, vss1=vss2=vss3=0v limits parameter symbol pins conditions vdd[v] min. typ. max. unit iih(1) ? ports 0, 1, 2 ? ports 7, 8 ? ports a, b, c ? res ? pwm0, pwm1 ? output disable ? pull-up resistor off ? vin=vdd (including the off-leak current of the output tr.) 2.5 - 5.5 1 iih(2) xt1, xt2 ? using as an input port ? vin=vdd 2.5 - 5.5 1 input high current iih(3) cf1 vin=vdd 2.5 - 5.5 15 iil(1) ? ports 0, 1, 2 ? ports 7, 8 ? ports a, b, c ? res ? pwm0, pwm1 ? output disable ? pull-up resistor off ? vin=vss (including the off-leak current of the output tr.) 2.5 - 5.5 -1 iil(2) xt1, xt2 ? using as an input port ? vin=vss 2.5 - 5.5 -1 input low current iil(3) cf1 vin=vss 2.5 - 5.5 -15 a ioh=-1.0ma 4.5 - 5.5 vdd-1 voh(1) ? ports 0, 1, 2 ? ports b, c voh(2) ? pwm0, pwm1 ioh=-0.1ma 2.5 - 5.5 vdd-0.5 voh(3) ioh=-5.0ma 4.5 - 5.5 vdd-1 voh(4) port a ioh=-0.4ma 2.5 - 5.5 vdd-0.5 output high voltage voh(5) p71-p73 ioh=-0.4ma 4.5 - 5.5 vdd-1 v vol(1) ? ports 0, 1, 2 ? ports b, c iol=10ma 4.5 - 5.5 1.5 vol(2) iol=1.6ma 4.5 - 5.5 0.4 vol(3) ? pwm0, pwm1 iol=1ma 2.5 - 5.5 0.4 vol(4) p00, p01 iol=30ma 4.5 - 5.5 1.5 vol(5) vol(6) ports 7, 8 iol=1ma 2.5 - 5.5 0.4 vol(7) iol=15ma 4.5 - 5.5 1.5 output low voltage vol(8) port a iol=2ma 2.5 - 5.5 0.4 v pull-up resistor rpu ? ports 0, 1, 2 ? port 7 ? ports a, b, c voh=0.9vdd 2.5 - 5.5 15 40 70 k ? hysteresis voltage vhis ? res ? port 1 ? port 2 ? port 7 2.5 - 5.5 0.1vdd v pin capacitance cp all pins ? a ll pins except the measured terminal : vin=vss ? f=1mhz ? ta=25c 2.5 - 5.5 10 pf
LC87F57C8A ver.1.00 17/27 4. serial input/output characteristics / ta=-20c to +70c, vss1=vss2=vss3=0v limits parameter symbol pins conditions vdd[v] min. typ. max. unit cycle t sck (1) 2 t sckl (1) 1 low level pulse width t sckla (1) 1 t sckh (1) 1 high level pulse width t sckha (1) sck0(p12) refer to figure 6 2.5 - 5.5 3(sio0) cycle t sck (2) 2 low level pulse width t sckl (2) 1 input clock high level pulse width t sckh (2) sck1(p15) refer to figure 6 2.5 - 5.5 1 cycle t sck (3) 4/3 t cyc t sckl (3) ? cmos output ? refer to figure 6 1/2 low level pulse width t sckla (2) sck0(p12) sio0 3/4 t sckh (3) 1/2 high level pulse width t sckha (2) sck0(p12), sck0(p12) sio0 2.5 - 5.5 2 tsck cycle t sck (4) 2 t cyc low level pulse width t sckl (4) 1/2 serial clock output clock high level pulse width t sckh (4) sck1(p15) ? cmos output ? refer to figure 6 2.5 - 5.5 1/2 tsck data set-up time tsdi 0.03 serial input data hold time thdi sb0(p11), sb1(p14), si0 si1 ? data set-up to si0clk ? data hold from si0clk ? refer to figure 6 2.5 - 5.5 0.03 serial output output delay time tdd0 so0(p10), so1(p13), sb0(p11), sb1(p14), ? data hold from si0clk ? time delay from si0clk trailing edge to the so data change in the open drain ? refer to figure 6 2.5 - 5.5 1/3tcyc +0.05 s
LC87F57C8A 18/27 ver.1.00 5. parallel input/output characteristics / ta=-20c to +70c, vss1=vss2=vss3=0v note: if port a terminals will be used as rs, wr , rd or cs , then it should be set to cmos format by option data. refer to figures 8 and 9 for parallel output timing. limits parameter symbol pins conditions vdd[v] min. typ. max. unit write cycle, read cycle tc(1) 2.5 - 5.5 1 tcyc tsa(1) ? wr (pa3), pb0-pb7 ? rd (pa4), pc0-pc7 2.5 - 5.5 1/3tcyc -30ns address set-up time tsa(2) rd (pa4), pc0-pc7 from address set-up until control signal changes 2.5 - 5.5 2/3tcyc -30ns tha(1) rd (pa4), pc0-pc7 from change of rd until address change 2.5 - 5.5 1/6tcyc tcyc & ns address hold time tha(2) wr (pa3), pc0-pc7 from change of wr until address change 2.5 - 5.5 5 ns tsrs(1) wr (pa3), rs(pa5), cs (pax) from change of rs, cs until change in wr 2.5 - 5.5 1/6tcyc -15ns tsrs(2) rd (pa4), rs(pa5) 2.5 - 5.5 1/6tcyc -15ns rs set-up time tsrs(3) rd (pa4), rs(pa5) from change of rs until change in rd 2.5 - 5.5 1/3tcyc -15ns tscs(1) rd (pa4), cs (pax) from change in cs until change in rd 2.5 - 5.5 1/3tcyc -15ns cs set-up time tscs(2) wr (pa3), cs (pax) from change in cs until change in wr 2.5 - 5.5 2/3tcyc -15ns tcyc & ns thrs(1) wr (pa3), rs(pa5) from change in wr until change in rs 2.5 - 5.5 0 ns thrs(2) rd (pa4), rs(pa5), cs (pax) 2.5 - 5.5 1/6tcyc tcyc & ns rs hold time thrs(3) rd (pa4), rs(pa5), cs (pax) from change in rd until change in rs, cs 2.5 - 5.5 0 ns thcs(1) rd (pa4), rs(pa5) from change in rd until change in cs 2.5 - 5.5 1/6tcyc tcyc & ns cs hold time thcs(2) wr (pa3), rs(pa5) from change in wr until change in cs 2.5 - 5.5 0 ns twrh(1) wr (pa3) 2.5 - 5.5 1/6tcyc -5ns 1/6 tcyc wr ?h? pulse width twrh(2) wr (pa3) 2.5 - 5.5 2/3tcyc -5ns 2/3 tcyc twrl(1) wr (pa3) 2.5 - 5.5 1/6tcyc -5ns 1/6 tcyc wr ?l? pulse width twrl(2) wr (pa3) 2.5 - 5.5 1/3tcyc -5ns 1/3 tcyc tcyc & ns (continued)
LC87F57C8A ver.1.00 19/27 limits parameter symbol pins conditions vdd[v] min. typ. max. unit trdh(1) rd (pa4) 2.5 - 5.5 1/6tcyc -5ns 1/6 tcyc rd ?h? pulse width trdh(2) rd (pa4) 2.5 - 5.5 1/3tcyc -5ns 1/3 tcyc trdl(1) rd (pa4) 2.5 - 5.5 1/3tcyc -5ns 1/3 tcyc rd ?l? pulse width trdl(2) rd (pa4) 2.5 - 5.5 1/2tcyc -5ns 1/2 tcyc tddt(1) rd (pa4), pb0-pb7 2.5 - 5.5 1/6tcyc -15ns data write maximum delay tddt(2) rd (pa4), pb0-pb7 the time delay allowed, from rd leading edge until input data set-up (note 1) 2.5 - 5.5 1/3tcyc -15ns tcyc & ns input data set-up time tsdtr(1) rd (pa4), pb0-pb7 from input data set- up to rd leading edge. (note 2) 2.5 - 5.5 40 ns input data hold time thdtr(1) rd (pa4), pb0-pb7 from rd leading edge until input data hold 2.5 - 5.5 0 ns tsdtw(1) rd (pa4), pb0-pb7 2.5 - 5.5 1/3tcyc -30ns output data set-up time tsdtw(2) rd (pa4), pb0-pb7 from output data set- up until wr leading edge 2.5 - 5.5 1/3tcyc -30ns tcyc & ns thdtw(1) 2.5 - 5.5 0 output data hold time thdtw(2) rd (pa4), pb0-pb7 from wr leading edge until output data hold 2.5 - 5.5 0 ns note 1 : time until incorrect data of low disappears. note 2 : incorrect data of low is not output in the period between trdl(1) - tddt(1). 6. pulse input conditions / ta=-20c to +70c, vss1=vss2=vss3=0v limits parameter symbol pins conditions vdd[v ] min. typ. max. unit tpih(1) tpil(1) int0(p70), int1(p71), int2(p72) int4(p20-p23) int5(p24-p27) ? interrupt acceptable ? timer 0 and 1 event input acceptable 2.5 - 5.5 1 tpih(2) tpil(2) int3(p73) (the noise rejection clock is selected to 1/1.) ? interrupt acceptable ? timer 0 event input acceptable 2.5 - 5.5 2 tpih(3) tpil(3) int3(p73) (the noise rejection clock is selected to 1/32.) ? interrupt acceptable ? timer 0 event input acceptable 2.5 - 5.5 64 tpih(4) tpil(4) int3(p73) (the noise rejection clock is selected to 1/128.) ? interrupt acceptable ? timer 0 event input acceptable 2.5 - 5.5 256 t cyc high/low level pulse width tpil(5) res reset acceptable 2.5 - 5.5 200 s
LC87F57C8A 20/27 ver.1.00 7. ad converter characteristics / ta=-20c to +70c, vss1=vss2=vss3=0v limits parameter symbol pins conditions vdd[v] min. typ. max. unit resolution n 3.0 - 5.5 8 bit absolute precision et (note 2) 3.0 - 5.5 1.5 lsb 4.5 - 5.5 15.10 (tcyc= 0.588s) 97.92 (tcyc= 3.06s) ad conversion time=32 t cyc (adcr2=0) (note 3) 3.0 - 5.5 31.36 (tcyc= 0.980s) 97.92 (tcyc= 3.06s) 4.5 - 5.5 18.82 (tcyc= 0.294s) 97.92 (tcyc= 1.53s) conversion time tcad ad conversion time=64 t cyc (adcr2=1) (note 3) 3.0 - 5.5 62.72 (tcyc= 0.980s) 97.92 (tcyc= 1.53s) s analog input voltage range vain 3.0 - 5.5 vss vdd v iainh vain=vdd 3.0 - 5.5 1 analog port input current iainl an0(p80) - an2(p82) an3(p03) - an7(p07) an8(p70) an9(p71) an10(xt1) an11(xt2) vain=vss 3.0 - 5.5 -1 a (note 2) absolute precision excludes the quantizing error (1/2 lsb). (note 3) the conversion time is the time from executing the ad conversion instruction to setting the complete digital conversion value in the register.
LC87F57C8A ver.1.00 21/27 8. current dissipation characteristics / ta=-20c to +70c, vss1=vss2=vss3=0v limits parameter symbol pins conditions vdd[v] min. typ. max. unit iddop(1) ? fmcf=10mhz by ceramic resonator ? fmx?tal=32.768khz by crystal oscillation ? system clock : cf oscillation (10mhz) ? internal rc oscillation stops ? frequency variable rc oscillation stops ? 1/1 divided 4.5 - 5.5 18 35 iddop(2) ? cf1=20mhz by external clock ? fmx?tal=32.768khz by crystal oscillation ? system clock : cf1 oscillation (20mhz) ? internal rc oscillation stops ? frequency variable rc oscillation stops ? 1/2 divided 2.5 - 5.5 19 36 iddop(3) 4.5 - 5.5 10 22 iddop(4) ? fmcf=5mhz by ceramic resonator ? fmx'tal=32.768khz by crystal oscillation ? system clock : cf oscillation (5mhz) ? internal rc oscillation stops ? frequency variable rc oscillation stops ? 1/1divided 2.5 - 4.5 5 15 iddop(5) 4.5 - 5.5 2 8 iddop(6) ? fmcf=0hz (when oscillation stops) ? fmx'tal=32.768khz by crystal oscillation ? system clock : rc oscillation ? frequency variable rc oscillation stops ? 1/2 divided 2.5 - 4.5 1 5 iddop(7) 4.5 ? 5.5 2.5 13 iddop(8) ? fmcf=0hz (when oscillation stops) ? fmx'al=32.768khz by crystal oscillation ? system clock :1mhz with frequency variable rc oscilatin ? internal rc oscillation stops ? 1/2 divided 2.5 - 4.5 1.8 9 ma iddop(9) 4.5 ? 5.5 50 150 current drain during basic operation (note 4) iddop(10) vdd1 =vdd2 =vdd3 ? fmcf=0hz (when oscillation stops) ? fmx'al=32.768khz by crystal oscillation ? system clock : x'tal oscillation (32.768khz) ? internal rc oscillation stops ? frequency variable rc oscillation stops ? 1/2 divided 2.5 - 4.5 30 120 a (continued)
LC87F57C8A 22/27 ver.1.00 limits parameter symbol pins conditions vdd[v] min. typ. max. unit iddhalt(1) ? halt mode ? fmcf=10mhz by ceramic resonator ? fmx?tal=32.768khz by crystal oscillation ? system clock : cf oscillation (10mhz) ? internal rc oscillation stops ? frequency variable rc oscillation stops ? 1/1 divided 4.5 - 5.5 4 10 iddhalt(2) ? halt mode ? cf1=20mhz by external clock ? fmx?tal=32.768khz by crystal oscillation ? system clock : cf1 oscillation (20mhz) ? internal rc oscillation stops ? frequency variable rc oscillation stops ? 1/2 divided 4.5 - 5.5 4.5 14 iddhalt(3) 4.5 - 5.5 2 5 iddhalt(4) ? halt mode ? fmcf=5mhz by ceramic resonator ? fmx?tal=32.768khz by crystal oscillation ? system clock : cf oscillation (5mhz) ? internal rc oscillation stops ? frequency variable rc oscillation stops ? 1/1divided 2.5 - 4.5 1 3.2 iddhalt(5) 4.5 - 5.5 0.5 1.5 iddhalt(6) ? halt mode ? fmcf=0hz (when oscillation stops) ? fmx?tal=32.768khz by crystal oscillation ? system clock : rc oscillation ? frequency variable rc oscillation stops ? 1/2 divided 2.5 - 4.5 0.3 1 iddhalt(7) 4.5 - 5.5 1.5 3.6 iddhalt(8) ? halt mode ? fmcf=0hz (when oscillation stops) ? fmx'tal=32.768khz by crystal oscillation ? system clock : 1mhz with frequency variable rc oscilatin ? internal rc oscillation stops ? 1/2 divided 2.5 - 4.5 1.3 3.3 ma iddhalt(9) 4.5 - 5.5 20 80 current drain in halt mode (note 4) iddhalt(10) vdd1 =vdd2 =vdd3 ? halt mode ? fmcf=0hz (when oscillation stops) ? fmx'tal=32.768khz by crystal oscillation ? system clock : x'tal oscillation (32.768khz) ? internal rc oscillation stops ? frequency variable rc oscillation stops ? 1/2 divided 2.5 - 4.5 10 50 a (continued)
LC87F57C8A ver.1.00 23/27 limits parameter symbol pins conditions vdd[v] min. typ. max. unit iddhold(1) 4.5 - 5.5 0.05 20 current drain during hold mode iddhold(2) vdd1 ? hold mode ? cf1=vdd or leave it open (when using external clock) 2.5 ? 4.5 0.01 15 a iddhold(3) 4.5 - 5.5 15 70 current drain during time-base clock hold mode iddhold(4) vdd1 ? time-base clock hold mode ? cf1=vdd or leave it open (when using external clock) ? fmx'tal=32.768khz by crystal oscillation 2.5 ? 4.5 5 40 a (note 4) the current of the output transistors and pull-up mos transistors are excluded. 9. f-rom write characteristics / ta=+10c to +55c, vss1=vss2=vss3=0v limits parameter symbol pins conditions vdd[v] min. typ. max. unit on-board writing current iddfw(1) vdd1 ? 128-byte writing ? including erase time current 4.5 - 5.5 30 65 ma writing time tfw(1) ? 128-byte writing ? including data erase time ? excluding time to fetch 128 byte data 4.5 - 5.5 5.0 10.0 ms
LC87F57C8A 24/27 ver.1.00 main system clock oscillation circuit characteristics the characteristics in the table bellow is based on the following conditions: 1. using the standard oscillation evaluation board s anyo has provided. 2. using the external peripheral parts with the indicated value. 3. the recommended circuit parameters for the peripheral parts are verified by the oscillator manufacturer. table 1. recommended circuit parameters for the main system clock using the ceramic resonator recommended circuit parameters oscillation stabilizing time frequency manufacturer oscillator c1 c2 rd1 operating supply voltage range typ max note csls10m0g53- b0 (15pf) (15pf) 0 ?? 4.5 ? 5.5v 0.03ms 0.30ms internal c1,c2 10mhz murata cstce10m0g52- r0 (10pf) (10pf) 0 ?? 4.5 ? 5.5v 0.03ms 0.30ms internal c1,c2 cstls5m00g53- b0 (15pf) (15pf) 0 ? 2.5 ? 5.5v 0.03ms 0.30ms internal c1,c2 5mhz murata cstcr5m00g53 -r0 (15pf) (15pf) 0 ? 2.5 ? 5.5v 0.03ms 0.30ms internal c1,c2 *the oscillation stabilizing time is a period until the oscillation becomes stable after vdd becomes higher than minimum operating voltage. (refer to figure4) subsystem clock oscillation circuit characteristics the characteristics in the table bellow is based on the following conditions: 1. using the standard oscillation evaluation board s anyo has provided. 2. using the external peripheral parts with the indicated value. 3. the recommended circuit parameters for the peripheral parts are verified by the oscillator manufacturer. table 2. recommended circuit parameters for the subsystem clock using the crystal oscillation recommended circuit parameters oscillation stabilizing time frequency manufacturer oscillator c3 c4 rf rd2 operating supply voltage range typ max note 32.768khz seiko epson mc-306 9pf 9pf open 820k ? 2.5 ? 5.5v 1.5s 3s *the oscillation stabilizing time is the period until the oscillation becomes stable, after executing the instruction which starts the sub-clock oscillator or after releasing a hold mode. (refer to figure4) (notes) since the oscillation frequency precision is a ffected by the circuit pattern, place the oscillation related parts as close to the oscillation pins as possible, using the shortest possible pattern length. figure 1 ceramic oscillation circuit figure 2 crystal oscillation circuit figure 3 ac timing point c1 c2 cf cf2 cf1 c3 rd2 c4 x?tal xt2 xt1 rf rd1 0.5vdd
LC87F57C8A ver.1.00 25/27 reset time and oscillation stabilizing time hold release signal and oscillation stabilizing time figure 4 oscillation stabilizing time power supply res# internal rc oscillation cf1 , cf2 xt1 , xt2 o perat i on mo d e reset time tmscf tmsxta u n fi xe d r eset i nstruct i on execut i on d vdd vdd li m i t gnd internal rc oscillation cf1 , cf2 xt1 , xt2 o perat i on mo d e hold re l ease s i gna l hold re l ease s i gna l valid tms cf tms x ta l hold halt
LC87F57C8A 26/27 ver.1.00 (note) select cres and rres value to assure that at least 200s reset time is generated after the vdd becomes higher than the minimum operating voltage. figure 5 reset circuit figure 6 serial input/output test condition figure 7 pulse input timing condition c res vdd r res res data ram transmission period (only sio0) di0 di7 di2 di3 di4 di5 di6 di8 do0 do7 do2 do3 do4 do5 do6 do8 di1 do1 si0clk: datain : dataout: dataout: datain: si0clk : dataout: datain: si0clk: tsck tsckl tsckh thdi tsdi tddo tsckla tsckha thdi tsdi tddo data ram transmission period (only sio0) tpil tpih
LC87F57C8A ver.1.00 27/27 ?e parallel input/output timing waveform ?f indirect setting, read mode note: if port a terminals will be used as rs, wr , rd or cs , then it should be set to cmos format by option data . ?e parallel input/output timing waveform ?f indirect setting, write mode note: if port a terminals will be used as rs, wr , rd or cs , then it should be set to cmos format by option data . figure 8 indirect mode: parallel timing diagram tsrs ( 1 ) adr/data : cs#: rs: wr#: rd#: datain tc ( 1 ) rea d cyc l e tsa ( 1 ) addr thrs ( 1 ) twrh ( 1 ) twrl ( 1 ) tsrs ( 2 ) trdl ( 1 ) thrs ( 2 ) trdh ( 1 ) tsdtr ( 1 ) tddt ( 1 ) thdtr ( 1 ) data h adr/data: cs#: rs: wr#: rd#: datain tc ( 1 ) wr i te cyc l e data addr tsa ( 1 ) tsrs ( 1 ) thrs ( 1 ) thdtw ( 1 ) thrs ( 3 ) tsrs ( 3 ) tsdtw ( 1 ) twrh ( 1 ) twrl ( 1 ) twrl ( 2 )
LC87F57C8A 28/27 ver.1.00 ?e parallel input/output timing waveform ?f direct setting, read mode note: if port a terminals will be used as rs, wr , rd or cs , then it should be set to cmos format by option data . ?e parallel input/output timing waveform ?f direct setting, write mode note: if port a terminals will be used as rs, wr , rd or cs , then it should be set to cmos format by option data . figure 9 direct mode: parallel input/output timing diagrams ?2002 sanyo data h tc ( 1 ) addr tsa ( 1 ) tscs ( 1 ) trdh ( 2 ) trdl ( 2 ) tddt ( 2 ) tsdtr ( 1 ) thdtr ( 1 ) tha ( 1 ) thcs ( 1 ) adr: cs#: data: wr#: rd#: datain tc ( 1 ) addr tsa ( 2 ) tscs ( 2 ) twrl ( 2 ) tsdtw ( 2 ) thdtw ( 2 ) tha ( 2 ) thcs ( 2 ) adr: cs#: data: wr#: rd#: datain: data twrh ( 2 ) rea d cyc l e wr i te cyc l e

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